ASSAY Information-flow schematic — engineering-drawing form Meridian · D+2 · step 8 · sheet 1/1 · rev v0.2
The demonstrator drawn as one apparatus — assessed knowledge piped in on the left, transformed through labelled stations (compile → score → relax → select), with the six honesty gates as inline decision valves and every assessed value on a gauge. Use the wizard to walk one heartbeat through the machine — press Next and watch the data flow, the gate fire, and the honest consequence land. Wireframe: line routing indicative, not final geometry.

KEY Reading the schematic

Seven typed connectors make every claim walkable both directions to a named owner (G3); six gates are where the discipline bites. A gate firing is the exhibit, not a fault.

Connectors (labelled flow lines)

compiled_intoknowledge → world channel
scored_fromchannel → verdict / score
cited_inverdict → relaxation / rationale
supersedesnewer answer overtakes older (K9→K5)
conteststwo answers irreconcilable (K12a↔K12b)
resolvesan adjudication closes a contest
waivesa J-3 waiver licenses a use (W-1)

Gates (decision valves ◇)

encoding lintbad answer refused at write — K10
waiverhard constraint needs a licence — K8/W-1
contest · G5contested never compiles — K12
compar. · G1cross-stamp greys, never lies
staleness · Fflags, no silent recompute
least-worst · G4infeasible → report, never empty

Stations & gauges

Knowledge — an assessed answer, owned by a named role
Process station — a seam service (compile / score / relax / select)
Verdict — a four-stop reading with its margin band
Refusal — an honest outcome, styled as such
Gauge — a band {lo,hi,unit}; the bar is the range, no midpoint

WALKTHROUGH One heartbeat, stepped through the machine

A scripted replay of the canonical walkthrough (vignette §9, oracle-consistent). It replays known results and says so — it does not compute. Press Next (or use ← →).
scripted replay · vignette §9
STEP0/6

—Opening state

Watch the delta recorder fill and the world stamp flip as you advance — a value never changes without a delta to name it (spec §2.2). Switch to Full schematic to see the whole apparatus at once.
① ASSESS · J-2 ② GATE ③ COMPILE · J-3/5 ④ SCORE ⑤ DECIDE · CMD K9 · KNOWLEDGE owner · J-2 Storm-surge maximum 0 3 m band 1.1–1.8 m reported · high supersedes K5 (revision, not deletion) K12 · KNOWLEDGE owner · J-2 Sea-mine stockpile K12a30–60 mines K12b140–220 mines ⇄ contested — cannot both stand K8 · KNOWLEDGE owner · J-2 Battery fire-control state claims a hard constraint (north approach) single-source needs waiver W-1 K10 · WRITE ATTEMPT J-2 Malformed answer assessed·low asserting a hard constraint — never becomes a K-object (see gate ②) compiled_into contested? G5 yes → block compile licensed? W-1 waives → well- formed? no ⛔ REFUSED AT WRITE reason: encoding_violation no assessed·low value may assert a hard constraint (DEC-9/15) ⛔ COMPILE REFUSED reason: contested_knowledge no channel is built from a contested pair (G5). resolve K12a/b first → then compile succeeds. SVC · CompileService J-3/5 COMPILE knowledge → world channels (sparse) consumes K9 (not superseded K5) WORLD STAMP · comparability G1 7f3a…c91 → 9b2e…44a on resolve channels tide/storm ch. threat ch. ·W-1 SVC · ScoreService J-3/5 SCORE channels → four-stop verdicts C1 marginal C2 marginal C4 tight scored_from feasible? G4 yes no · R3m SVC · RelaxService least-worst · G4 · never empty RELAX — least-worst frontier inclusion-minimal correction sets, ranked least-worst-first · tie_break stated rank 1should sacrifice C4 C4 violated rank 2should sacrifice C3 C3 violated rank 3must · last sacrifice C2 C2 violated tie_break: same-tier C3 / C4 ordered by a stated, content-neutral rule — never a value judgement (DEC-19). cited_in RATIONALE decided_by · CMD SELECT — the decision P2 chosen · cites its verdicts walks back to a named owner (G3) STALENESS BUS · thesis F · flags, never a silent recompute ⚑ SCRIPTED — Stage 6, not yet computed K9 superseding K5 fans out to flag exactly the K5-dependent artefacts — nothing else, nothing silent: ⚑ P1 · C2 ⚑ P2 · C1 ⚑ P2 · C2 supersedes K5 ⤳ fan-out DELTA RECORDER · S4 BRIDGE — watches, never writes · append-only, stamped seq 42–45 seq 45Plannercompile → world 9b2e…44a · handful P1–P4 re-scored · stamp flipped seq 44J-2resolve K12a → surviving K12b · resolves edge · contest closed seq 43J-2contest K12a ⇄ K12b · compile blocked (G5) · no new world stamp seq 42J-2supersede K5 → K9 · staleness fan-out: P1·C2, P2·C1, P2·C2 (scripted) ASSAY · INFORMATION-FLOW SCHEMATIC TABLEAUMeridian · D+2 · step 8 WORLD7f3a…→9b2e… SEED42 SHEET / REV1/1 · v0.2 FICTION — the Meridian Archipelago is an engineered scenario (DEC-8). No real operational picture.

What the walkthrough shows

Six beats of the canonical heartbeat. J-2 supersedes K5 with a fresher read (the staleness bus flags exactly what leaned on the old answer); contests K12, so the contest gate (G5) refuses compile; resolves it; the planner recompiles to a new stamped world; the least-worst gate (G4) opens relax because R3m is infeasible; the commander selects. A malformed K10 write never enters — the encoding lint refuses it at the door.

Switch to Full schematic to see the whole apparatus at once — the walkthrough is that same drawing, revealed one honest consequence at a time.

Honesty, kept on the face of the drawing

Bands stay banded. Every assessed value is a gauge with lo–hi unit and its provenance chip; no bare assessed scalar appears. Gates are the exhibit — each refusal is drawn as an honest outcome. Recompute is attributable: the stamp flips and a delta lands together — never one without the other (spec §2.2).

Scripted where not yet computed. The tour replays the walkthrough's oracle-consistent results and says so; the staleness fan-out is marked scripted — thesis F is Stage 6, not-started (research note 07 §5). It will drive the real seam once Stage 6 lands.

Alternative, not replacement. A second idiom for assay-flow-infographic-spec.md, alongside the role-swimlane wireframe — offered so the design direction can be chosen from concrete artefacts.